1. Field of the Invention
This invention relates to methods for etching semiconductor substrates, and more particularly to double gate recess etching methods used in the fabrication of GaAs microwave monolithic integrated circuit (MMIC) chips.
2. Description of the Related Art
GaAs circuits are used primarily for radar and communications applications, both in power amplifiers for transmission and in receive circuitry. A higher degree of amplification can be achieved with metal-semiconductor field effect transistors (MESFETs) if the gate is recessed into the GaAs chip, rather than formed on its surface. This type of structure is illustrated in FIG. 1, in which a portion of a GaAs substrate is shown with n+ doped source and drain regions 4 and 6, respective source and drain contacts S and D, and an n-type channel region 8 between the source and drain regions. A single gate recess 9 is formed from the upper substrate surface into the channel region, between and separated from the source and drain region 4, 6. A metallized gate contact G is established to the floor of the recess.
The dimensions of the recess and the gate contact are important factors in determining the characteristics of a power amplifier that employs a gate recess profile MESFET. Specifically, the dimension "a" between the edges of the gate contact G (in the direction of the channel current flow) and the adjacent edges of the recess floor influences the amplifier's operation. In general, a large dimension "a" results in lower efficiency and lower output power, but a higher breakdown voltage level. Depending upon the ultimate application for the transistor, the dimension "a" is selected to yield an optimum tradeoff among these three performance factors.
One disadvantage associated with the single gate recess profile of FIG. 1 is its increased gate-to-drain feedback capacitance as compared to planer FET structures. Gate-to-drain feedback capacitance reduces the FET's gain and makes it less stable by decreasing the isolation between the input and the output. To limit the FET's feedback capacitance and increase its breakdown voltage in a gate recess structure, a second wider recess, the channel recess, is employed so that the depth of the gate recess below the channel recess can be reduced relative to the depth of the gate recess in FIG. 1. The FET's feedback capacitance is thereby reduced while the total gate recess depth is increased to improve the transistor gain. The structure as described, referred to as a double gate recess profile and shown in FIG. 2, has been fabricated in a two step process, in which a shallow, wide channel recess 10 is etched with a first photoresist mask having an opening indicated by m1, followed by replacing the first mask with a second photoresist mask having an opening that is indicated by m2 and through which a narrow gate recess 11 is etched using the same etchant. This technique is described in DiLorenzo, ed., GaAs FET Principles and Technology, Artech House, Inc., 1982, pages 286-289 and Williams, Gallium Arsenide Processing Techniques, Artech House, Inc., 1984, pages 69-70.
A problem with the double-mask method of forming a double gate recess profile is the difficulty of properly aligning the masks used in forming the gate and channel recesses. Referring to FIG. 2, ideally the gate recess 11 is established in the middle of the channel recess 10. The widths of the channel recess's two planar portions, which lie above and bound the gate recess 11 and are indicated by X1 and X2, would thus be approximately equal. Making X1 and X2 equal is important in providing a balance between the FET's breakdown voltage and its source and gate-to-drain resistances. Since the first and second masks are often not exactly aligned, X1 and X2 usually are not equal. Also, the double-mask process is costly because two mask layers must be established.
Two types of etchants, ammonia hydroxide (NH.sub.4 OH) and phosphoric acid (H.sub.3 PO.sub.4), are currently in popular use for etching recesses in GaAs. FIG. 3 illustrates the etch process for NH.sub.4 OH, in which a partially completed MESFET has been coated with a layer of photoresist 12. An opening 14 is provided in the photoresist over the intended gate recess area, with a photoresist overhang 16 extending over part of the upper portion of the opening 14 to provide a reduced diameter entrance opening 18. The amount of overhang effects the size of the gate recess, and also of the metallized gate contact that is added after the recess has been established. NH.sub.4 OH produces an isotropic etch in which the gate recess floor 20 is narrower than the photoresist opening 14. The H.sub.3 PO.sub.4 process, not shown, performs an anisotropic etch to produce a gate recess floor width that is approximately equal to the photoresist opening width.